Throughout the prior art, metal gate integration has proven difficult to achieve in a conventional process flow for MOS transistors. Most metal gate materials interact with the gate dielectric during the high temperature processing needed for source/drain (S/D) junction activation anneals. The need to keep the metal gate stack from receiving high temperature anneals has lead to the development of the “gate last” or “replacement gate” process for which the gate stack is fabricated last and remains below 500° C. during subsequent processing. Although the prior art replacement gate process increases the number of material choices for a metal gate, the process complexity and cost increases.
It is known in the prior art to form self-aligned silicided metal gates from a polysilicon gate using the processing steps shown, for example, in FIGS. 1A-1D. Specifically, the prior art process begins with providing the structure shown in FIG. 1A, which structure includes a semiconductor substrate 12, an isolation region 15, gate regions 16L and 16R, a gate dielectric 18, a polySi gate conductor 20 and a cap layer 22. Spacers 24 are located on each gate region as well. As shown, the source/drain implants are performed with the cap layer 22 atop the polySi conductor 20. Next, the cap layer 22 is non-selectively removed, as shown in FIG. 1B, and then a silicide metal 105 such as Ni is deposited on the entire structure providing the structure shown in FIG. 1C. An optional oxygen diffusion barrier layer can be formed atop the silicide metal and then annealing is performed to cause reaction between the polySi and silicide metal. Depending on the metal, a low resistivity silicide can be formed utilizing a single anneal. After the single anneal, any unreacted metal and the optional oxygen diffusion barrier is removed, and if needed, a second anneal may be performed. FIG. 1D shows the structure after the salicide process in which silicided source/drain regions 100 and metal silicide gate 102 are formed. In this prior art process, gate and source/drain silicidation occurs simultaneously.
As shown, this prior art process forms thick metal silicide gates and thick source/drain silicides, each having a thickness of approximately 100 nm. This can be problematic for a few reasons. Firstly, the silicide can extend underneath the gate and short the device. Secondly, such a thick source/drain silicide can also be problematic given the recess of the isolation regions of the device caused by the non-selective removal of the cap layer from the gate. Specifically, the silicide in this prior art process can short across devices separated by narrow isolation regions. Thirdly, the thick silicide may consume the silicon in the extension regions under the spacers leading to poor device performance. Hence, methods that produce a thick and fully silicided metal gate and a much thinner source/drain silicide are needed. In addition, the silicide in this prior art process can also contact the implanted well regions of the device thereby shorting the device.